geometry process details principal device types cmldm8002a cmpdm8002a ctldm8002a-m621 gross die per 6 inch wafer 62,600 process CP764X small signal mosfet transistor p-channel enhancement-mode transistor chip process epitaxial planar die size 21.7 x 17.7 mils die thickness 5.5 mils gate bonding pad area 4.7 x 4.7 mils source bonding pad area 6.1 x 7.9 mils top side metalization al-si - 35,000? back side metalization au - 12,000? www.centralsemi.com r1 (22-march 2010)
process CP764X typical electrical characteristics www.centralsemi.com r1 (22-march 2010)
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